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ISL97672A
Low-Voltage Operations
The ISL97672A VIN pin can be separately biased from the LED
power input to allow low-voltage operation. For systems that have
V IN = 2.7~26.5V
Q1 (OPTIONAL)
45V*, 6 x 50mA
2 VIN
CH2 12
3 EN
only a single supply, V OUT can be tied to the driver VIN pin to allow
initial start-up (Figure 22). The circuit works as follows: when the
input voltage is available and the device is not enabled, V OUT
follows V IN with a Schottky diode voltage drop. The V OUT
boot-strapped to the VIN pin allows initial start-up, once the part
is enabled. Once the driver starts up with V OUT regulating to the
target, the VIN pin voltage also increases. As long as V OUT does
not exceed 26.5V and the extra power loss on V IN is acceptable,
this configuration can be used for input voltage as low as 3.0V.
The Fault Protection FET feature cannot be used in this
configuration.
VBIAS = 5V~12V
ISL97672A
1 FAULT
LX 20
OVP 16
4 VDC
PGND 19
6 FLAG CH0 10
CH1 11
5 PWM
CH3 13
17 RSET CH4 14
For systems that have dual supplies, the VIN pin can be biased
from 5V to 12V, while input voltage can be as low as 2.7V
(Figure 23). In this configuration, VBIAS must be greater than or
8 FSW
9 AGND
CH5 15
COMP 18
*V IN > 12V
equal to VIN to use the fault FET.
FIGURE 23. DUAL SUPPLY 2.7V OPERATION
V IN = 3V~21V
ISL97672A
1 FAULT
26.5V*, 6 x 50mA
Compensation
The ISL97672A incorporates a transconductance amplifier in its
feedback path to allow the user to optimize boost stability and
transient response. The ISL97672A uses current mode control
2 VIN
4 VDC
6 FLAG
LX 20
OVP 16
PGND 19
CH0 10
architecture, which has a fast current sense loop and a slow
voltage feedback loop. The fast current feedback loop does not
require any compensation, but for stable operation, the slow
voltage loop must be compensated. The compensation is a
series of Rc, Cc1 network from COMP pin to ground, with an
optional Cc2 capacitor connected between the COMP pin and
5 PWM
3 EN
17 RSET
8 FSW
9 AGND
CH1 11
CH2 12
CH3 13
CH4 14
CH5 15
COMP 18
*V IN > 12V
ground. The Rc sets the high-frequency integrator gain for fast
transient response, and the Cc1 sets the integrator zero to
ensure loop stability. For most applications, the component
values in Figure 24 can be used: Rc is 10k ? and Cc1 is 3.3nF.
Depending upon the PCB layout, for stability, a Cc2 of 390pF may
be needed to create a pole to cancel the output capacitor ESR’s
zero effect.
FIGURE 22. SINGLE SUPPLY 3.0V OPERATION
Cc1
3.3nF
Rc 10k
Cc2
390pF
COMP
FIGURE 24. COMPENSATION CIRCUIT
For additional products, see www.intersil.com/product_tree
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
14
FN7710.3
November 22, 2013
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